High data reliability, high speed memory access, and reduced chip size are features that are demanded from semiconductor memory. In recent years, deterioration due to hot carrier injection has become a critical issue in the improvement of high data reliability. The term “hot carrier” refers to an electron or a hole in the substrate of a metal-oxide-semiconductor (MOS) device that has sufficient kinetic energy to free itself from an interface state. When hot carriers are produced as a result of very high fields in a drain region of a MOS field-effect transistor, the hot carriers may compromise operations of the MOS device by generating charged defects in an oxide layer, and by degrading an oxide and Si—SiO2 interface. These effects may create a reliability problem. The hot carriers may also generate unwanted current components.
As preventive measures against hot carrier injection, high threshold voltage (Vt) transistors may be used in order to provide an extra voltage gap around a target transistor likely to have hot carrier injection between a positive power supply node and a ground/negative voltage node. For example, U.S. Pat. No. 4,740,713 describes a system having a longitudinally stacked configuration of transistors, including a transistor having a high Vt in order to reduce a drain-source voltage (Vds) between a drain node and a source node of the target transistor that may cause the hot carrier injection. FIG. 1A are circuit diagrams of examples of inverter circuits with and without the transistor having the high Vt. FIG. 1B includes graphs showing drain-source voltages of target transistors in the inverter circuits of FIG. 1A. For example, a first inverter circuit 10 includes a power-supply terminal 101 providing a first voltage VCCP, a ground terminal 102 providing a second voltage VSS, a first transistor 11 having a source node coupled to the power-supply terminal 101 and a second transistor 12 that is the target transistor having a source node coupled to the ground terminal 102. In the first inverter circuit 10, Vds of the second transistor 12, that is “VCCP−VSS” as shown in a left graph of FIG. 1B, may be significantly greater than the average and may cause the hot carrier injection in the second transistor 12. In another example, a second inverter circuit 10′ includes a power-supply terminal 101, a ground terminal 102, a first transistor 11′ having a source node coupled to the power-supply terminal 101, a second transistor 12′ that is a target transistor having a source node coupled to the ground terminal 102 and a third transistor 13 having the high Vt and coupled between the first transistor 11′ and the second transistor 12′. In the second inverter circuit 10′, Vds of the second transistor 12′ becomes “(VCCP-Vt)-VSS” as shown in a right graph of FIG. 1B. Thus, the Vds may be lower compared to not including the third transistor 13, and may prevent hot carrier injection. The above countermeasure inverter circuit 10′ in FIG. 1A, however, increases a chip size. Consequently, another countermeasure circuit for the deterioration due to the hot carrier injection without requiring a significantly larger area may be desired.